1. Field of the Invention
The present invention relates to a reference voltage circuit using an enhancement type NMOS transistor (E-type NMOS transistor) and a depletion type NMOS transistor (D-type NMOS transistor).
2. Description of the Related Art
In recent years, for example, in an integrated circuit (IC) for protecting a lithium battery, the lithium battery is required to be charged in a temperature range in which the lithium battery is useable, that is, in a range up to an over-charge detection voltage of the lithium battery which is specified by the Electrical Appliance and Material Safety Law in Japan. In a case where a temperature characteristic of the overcharge detection voltage is poor, when the overcharge detection voltage becomes lower because of a change in temperature, the lithium battery is not completely charged, to thereby shorten an operating time of an electronic device using the lithium battery. When the overcharge detection voltage becomes higher, a battery voltage of the lithium battery exceeds the overcharge detection voltage, and hence fire accidents are highly likely to occur. Therefore, an IC in which the temperature characteristic of the overcharge detection voltage is excellent is desired. In other words, the overcharge detection voltage is a reference voltage output from a reference voltage circuit included in the IC, and hence an IC in which the temperature characteristic of the reference voltage is excellent is desired.
Even in a case of an IC for another use, when the temperature characteristic of the reference voltage is poor, it is likely to cause a defect, for example, an erroneous operation because of the change in temperature. Therefore, an IC in which the temperature characteristic of the reference voltage is excellent is also desired.
A conventional reference voltage circuit is described. FIG. 8 illustrates the conventional reference voltage circuit. FIG. 9 illustrates a conventional relationship between a reference voltage and a temperature.
When a gate-source voltage of a D-type NMOS transistor 91 is denoted by VGD, a threshold voltage thereof is denoted by VTD, and a K-value (drive capability) thereof is denoted by KD, a drain current ID is expressed by the following Expression (1).ID=KD·(VGD−VTD)2  (1)
A gate of the D-type NMOS transistor 91 is connected to a source thereof, and hence VGD=0. Therefore, the following Expression (2) holds.ID=KD·(0−VTD)2=KD·(|VTD|)2  (2)
When a gate-source voltage of an E-type NMOS transistor 92 is denoted by VGE, a threshold voltage thereof is denoted by VTE, and a K-value thereof is denoted by KE, a drain current IE is expressed by the following Expression (3).IE=KE·(VGE−VTE)2  (3)
The same drain current flows into the D-type NMOS transistor 91 and the E-type NMOS transistor 92, and hence ID=IE. Therefore, the following Expression (4) holds. From Expression (4), the following Expression (5) holds.ID=IE=KD·(|VTD|)2=KE·(VGE−VTE)2  (4)VGE=VTE+(KD/KE)1/2·|VTD|  (5)
The E-type NMOS transistor 92 is saturation-connected, and hence a gate voltage is equal to a drain voltage. The drain voltage corresponds to a reference voltage Vref. Therefore, the reference voltage Vref is expressed by the following Expression (6).VGE=Vref=VTE+(KD/KE)1/2·|VTD|  (6)
The K-values of the D-type NMOS transistor 91 and the E-type NMOS transistor 92 are circuit-designed as appropriate so that the following Expression (7) holds in a case where (KD/KE)1/2=α to improve the temperature characteristic of the reference voltage Vref, that is, to suppress a change in tilt of the reference voltage Vref with respect to a temperature.
                                          ⅆ            Vref                                ⅆ                          T                              T                =                                  25                  ⁢                  °                  ⁢                                                                          ⁢                                      C                    .                                                                                      =                                                            ⅆ                VTE                                            ⅆ                                  T                                      T                    =                                          25                      ⁢                      °                      ⁢                                                                                          ⁢                                              C                        .                                                                                                                  +                                                            ⅆ                  α                                ⁢                                                    VTD                                                                              ⅆ                                  T                                      T                    =                                          25                      ⁢                      °                      ⁢                                                                                          ⁢                                              C                        .                                                                                                                          =          0                                    (        7        )            
However, as indicated by a solid line 201 of FIG. 9, the reference voltage Vref curves in a substantially quadric manner with respect to a temperature. In other words, the following Expression (8) does not become zero.
                                                        ⅆ              2                        ⁢            Vref                                ⅆ                          T              2                                      =                                                            ⅆ                2                            ⁢              VTE                                      ⅆ                              T                2                                              +                                                                      ⅆ                  2                                ⁢                α                            ⁢                                              VTD                                                                    ⅆ                              T                2                                                                        (        8        )            
When the IC including the reference voltage circuit is in mass production, threshold voltages vary because of various factors. It has been known that a variation in threshold voltage of the D-type NMOS transistor 91 is larger than a variation in threshold voltage of the E-type NMOS transistor 92. That is, the first term and second term of the right side of Expression (7) vary, and hence Expression (7) does not hold. Therefore, as indicated by a dotted line 202 and a broken line 203 which are illustrated in FIG. 9, the reference voltage changes with respect to a temperature (see, for example, Japanese Patent Application Laid-open No. Hei 08-335122 (FIG. 2)).
In order to solve the problem described above, there has been proposed a technology in which a temperature correction circuit for the reference voltage Vref output from the reference voltage circuit is added to improve the temperature characteristic of the reference voltage Vref (see, for example, Japanese Patent Application Laid-open No. Hei 11-134051 (FIG. 1)).
When the technology disclosed in Japanese Patent Application Laid-open No. Hei 11-134051 is employed, the temperature characteristic of the reference voltage Vref is improved. However, the temperature correction circuit for the reference voltage Vref output from the reference voltage circuit is added separate from the reference voltage circuit, and hence a circuit scale is increased by the addition.